1. Field of the Invention
The present invention generally relates to a high-speed analog-to-digital converter, and more particularly relates to a precise self-calibrating, low power and high-speed analog-to-digital converter, which may be utilized for high speed wire/wireless receivers, or testing and measurement systems.
2. Description of the Prior Art
Advance in process technology coupled with aggressive circuit design, has led to an explosive growth in speed and circuits integration complexity. For these improvements, to enhance overall system performance, the communication speed between systems and integrated circuits must increase accordingly. As the demand of mass transmission increases, it has become an inevitable trend to transmit at higher data rate in finite channels. Naturally, the importance of high-speed link technology is on the rise.
Today, the analog-to-digital (hereinafter ADC) is build in various consumer products, especially to those transforming the analog signals to digital signals and sending data to the processor for computing information, including wireless device, cell phone, handheld personnel devices etc. Usually in normal working situation the ADC consumes the power proportionally, so in the power-by-batteries handheld electronic devices the power consumption in each component must be considered carefully.
ADCs come in several basic architectures, and many variations exist for each type. Each type has advantages and disadvantages with a particular combination of speed, accuracy, and power consumption. They all fit into a particular application. For example, a digital oscilloscope needs high digitizing speeds but may sacrifice resolution, so it uses flash converters. Some communication devices use pipeline ADCs, which provide better solution than flash converters, but at the expense of speed. General data-acquisition equipments usually adopt successive approximation registers. And audio coders use sigma-delta converters for high resolution.
The conventional flash architecture is the simplest and fastest analog-to-digital converter. In a typical flash ADC, the analog input signal is simultaneously compared to reference voltages by a string of comparator circuits. As the input voltage increases, the comparators set their outputs to logic 1, starting with the lowest comparator. Think of the flash converters as being like a mercury thermometer. As temperature increases, the mercury rises. Likewise, as the input voltage rises, comparators referenced to higher voltages set their outputs from 0 to 1. The thermometer code is encoded into binary code. The reference voltages are provided by connecting to a resistor string to generate the monotonic increase of reference voltages of full scale.
The conventional flash ADC is considered to realize the fastest conversion rate but it suffers from not only larger chip size and larger power dissipation, but also lower dynamic performance due to large input capacitance. For an N-bit flash ADC, 2N−1 comparators and 2N resistors are required. Flash ADCs are fast, but they have drawbacks. When resolution increases, the amounts of comparators and resistors grow exponentially, and they consume considerable power. As a result, most flash ADC studies have been focused on less than 8-bit resolution.
The U.S. Pat. No. 5,237,326 discloses a flash type ADC for converting analog signals to N-bit digital signals, and it includes 2N−1 comparators having different threshold values in a sequential order which perform full parallel-connected comparison. Buffer-amplifiers buffer the outputs of the respective comparators and a priority encoder encodes the outputs of the comparators. Jincheol Yoo, in “A 1-GSPS CMOS Flash A/D Converter for System-on-Chip Application”, presents an ultra fast CMOS flash A/D converter design. Although the featured A/D converter is designed in CMOS, the performance is compatible to that of GaAs technology currently available. To achieve high-speed in CMOS, the featured A/D converter utilizes the Threshold Inverter Quantization (TIQ) technique. A 6-bit TIQ based flash A/D converter was designed with the 0.25 μm standard CMOS technology parameter. It operates with sampling rates up to 1 GSPS, dissipates 66.87 mW of power at 2.5 V, and occupies 0.013-mm2 area. The proposed A/D converter is suitable for System-on-Chip (SOC) applications in wireless products and other ultra high-speed applications.